___________________________________________________ ___________________________________________________ _______________________ _________________ dsc2033 page 1 mk -q-b-p-d-120426 09 -2 low-jitter configurable dual lvds oscillator dsc 20 33 general description the dsc20 33 series of high performance dual output lvds oscillators utilize a proven silicon mems technology to provide excellent jitter and stability while incorporating additional device functionality. the two outputs are controlled by separate supply voltages to allow for high output isolation. the frequencies of the outputs can be identical or independently derived from a common pll frequency source. the dsc20 33 has provision for up to eight user- defined pre-programmed, pin-selectable output frequency combinations. dsc2033 is packaged in a 14-pin 3.2x2.5 mm qfn package and available in temperature grades from ext. commercial to industrial. block diagram features ? low rms phase jitter: <1 ps (typ) ? high stability: 10, 25, 50 ppm ? wide temperature range o industrial: -40 to 85 c o ext. commercial: -20 to 70 c ? high supply noise rejection: -50 dbc ? two independent lvds outputs ? pin -selectable configurations o 3-bit output frequency combinations ? short lead times: 2 weeks ? wide freq. range: o lvds output: 2.3 C 460 mhz ? miniature footprint of 3.2x2.5mm ? excellent shock & vibration immunity o qualified to mil-std- 883 ? high reliability o 20x better mtf than quartz oscillators ? supply range of 2.25 to 3.6 v ? lead free & rohs compliant applications ? storage area networks o sata, sas, fibre channel ? passive optical networks o epon, 10g-epon, gpon, 10g- pon ? ethernet o 1g, 10gbase-t/kr/lr/sr, and fcoe ? hd/sd/sdi video & surveillance ? pc i express downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc2033 page 2 mk -q-b-p-d-120426 09 -2 dsc20 33 low -jitter configurable dual lvds oscillator pin description pin no. pin name pin type description 1 enable i enables outputs when high and disables when low 2 nc na leave unconnected or grounded 3 nc na leave unconnected or grounded 4 gnd power ground 5 fs0 i least significant bit for frequency selection 6 fs1 i middle bit for frequency selection 7 fs2 i most significant bit for frequency selection 8 output1+ o positive lv ds output 1 9 output1- o negative lv ds output 1 10 output 2- o negative lvds output 2 11 output 2+ o positive lvds output 2 12 vdd2 power power supply 2 for lvds output 2 13 vdd power power supply 14 nc na leave unconnected or grounded operational description the dsc 2033 is a dual output lv ds oscillator consisting of a mems resonator and a support pll ic . the two outputs are generated through independent 8-bit programmable dividers from the output of the internal pll . two constraints are imposed on the output frequencies: 1) f 2 =m x f 1 /n , where m and n are even integers between 4 and 254, 2) 1.2ghz < n x f 2 < 1.7ghz. the actual frequencies output by the dsc20 33 are controlled by an internal pre-programmed memory (otp). this memory stores all coefficients required by the pll for up to eight different frequency combinations. three control pins (fs0 C fs2) select the output frequency combination. discera supports customer defined versions of the dsc2033. standard frequency options are described in in the following sections. when enable (pin 1) is floated or connected to v dd , the dsc20 33 is in operational mode. driving enable to ground will tri-state both output drivers (hi-impedance mode). output clock frequencies table 1 lists the standard frequency configurations and the associated ordering information to b e used in conjunction with the ordering code above. customer defined combinations are available. table 1. pre-programmed pin-selectable output frequency combinations ordering info freq (mhz) freq select bits [fs2, fs1, fs0] C default is [ 111 ] 000 001 010 011 100 101 110 111 g 000 1 f out1 148.5 156.25 150 125 125 100 100 400 f out2 74.25 125 125 25 50 50 75 200 g0002 f out1 100 125 0 0 0 0 0 0 f out1 100 125 0 0 0 0 0 0 g xxxx f out1 contact factory for additional configurations. f out2 frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and the device will output the associated frequency highlighted in bold . downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc2033 page 3 mk -q-b-p-d-120426 09 -2 dsc20 33 low -jitter configurable dual lvds oscillator absolute maximum ratings item min max unit condition supply voltage -0.3 +4.0 v input voltage -0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40 sec max. esd hbm mm cdm - 4000 400 1500 v note: 1000+ years of data retention on internal memory ordering code specifications (unless specified otherwise: t=25 c) notes: 1. pin 4 v dd should be filtered with 0.01uf capacitor. 2. output is enabled if enable pad is floated or not connecte d. 3. t su is time to 100ppm stable output frequency after v dd is applied and outputs are enabled. 4. output waveform and test circuit figures below define the parameters. 5. period jitter includes crosstalk from adjacent output. parameter condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current i dd en pin low C outputs are disabled 21 23 ma supply current 2 i dd en pin high C outputs are enabled r l = 10 0 , f o1 =f o2 =156.25 mhz 38 ma frequency stability f includes frequency variations due to initial tolerance, temp. and power supply voltage 10 25 50 ppm aging f 1 year @ 25c 5 ppm startup time 3 t su t= 25c 5 ms input logic levels input logic high input logic low v ih v il 0.75xv dd - - 0.25xv dd v output disable time 4 t da 5 ns output enable time t en 20 ns pull-up resistor 2 pull-up exists on all digital io 40 k lv ds outputs output offset voltage r=100 differential 1.125 1.4 v delta offset voltage 50 mv pk to pk output swing single-ended 350 mv output transition time 4 rise time fall time t r t f 20% to 80% r l = 10 0 , c l = 2pf (to gnd) 2 00 350 ps frequency f 0 single frequency 2.3 4 60 mhz output duty cycle sym differential 48 52 % period jitter 5 j per f o1 =f o2 =156.25 mhz 2.5 ps rms integrated phase noise j cc 200khz to 20mhz @156.25mhz 100khz to 20mhz @156.25mhz 12khz to 20mhz @156.25mhz 0.28 0.4 1. 7 2 ps rms dsc2033 xxxxx freq (mhz) see freq. table - packing t: tape & reel : tube f i 2 package f: 3.2x2.5mm temp range e: -20 to 70 i: -40 to 85 stability 1: 50ppm 2: 25ppm 5: 10ppm t downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc2033 page 4 mk -q-b-p-d-120426 09 -2 dsc20 33 low -jitter configurable dual lvds oscillator nominal performance parameters (unless specified otherwise: t=25 c, v dd =3.3 v) lvds phase jitter (integrated phase noise) output waveform: lvds 0.0 0.5 1.0 1.5 2.0 2.5 0 200 400 600 800 1000 phase jitter (ps rms) low -end of integration bw: x khz to 20 mhz 156mhz-lvds 212mhz-lvds 320mhz-lvds 410mhz-lvds v il 1/ f o output enable t da t en t f t r v ih 80 % 20% 50% output 830 mv 350 mv downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc2033 page 5 mk -q-b-p-d-120426 09 -2 dsc20 33 low -jitter configurable dual lvds oscillator solder reflow profile package dimensions 3.2 x 2.5 mm 14 lead plastic package disclaimer: micrel makes no representations or warranties with respec t to the accuracy or completeness of the information fu rnished in this data sheet. this information is not intended as a warranty and micrel does not assum e responsibility for its use. micrel reserves the right t o change circuitry, specifications and descriptions at any time without notice. no license, wheth er express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrel s terms and conditions of sale for such products, micrel a ssumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or us e of micrel products including liability or warranties relating t o fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. micrel products are not designed or authorized for use a s components in life support appliances, devices or syste ms where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably ex pected to result in a significant injury to the user. a pu rchasers use or sale of micrel products for use in life support appliances , devices or systems is a purchasers own risk and pu rchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. micrel, inc. 2180 fortune drive, san jose, california 95131 usa phone: +1 (408) 944-0800 fax: +1 (408) 474 -1000 email: hbwhelp@micrel.com www.micrel.com msl 1 @ 260 c refer to jstd-020c ramp-up rate (200 c to peak temp) 3 c/sec max. preheat time 150 c to 200 c 60 -180 sec time maintained above 217 c 60 -150 sec peak temperature 255-260 c time within 5 c of actual peak 20 -40 sec ramp-down rate 6 c/sec max. time 25 c to peak temperature 8 min max. 60 -150 sec 20 - 40 sec 60 -180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60 -150 sec 20 - 40 sec 60 -180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60 -150 sec 20 - 40 sec 60 -180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. downloaded from: http:///
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